Custom Code/PowerPC Assembly Cheatsheet/Special Purpose Registers: Difference between revisions

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{{DISPLAYTITLE:PowerPC Special Purpose Registers}}
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{| class="wikitable mw-collapsible mw-collapsed" style="min-width: 200px"
|+Condition Register (CR)
!Sub-register
!Name
!Attributes
!Bits
!Purpose
|-
| rowspan="4" |cr0
| rowspan="4" |Condition Register Bitfield 0
(Integer Op. Result CR)
| rowspan="4" |Volatile
|1
|Less Than (LT) bit. Set to 1 if the result of the last integer instruction was negative.
|-
|1
|Greater Than (GT) bit. Set to 1 if the result of the last integer instruction was positive and non-zero.
|-
|1
|Equal (EQ) bit. Set to 1 if the result of the last integer instruction was zero.
|-
|1
|Summary Overflow (SO) bit. Copy of XER[SO] after the last integer instruction. ''Refer to XER table for details.''
|-
| rowspan="4" |cr1
| rowspan="4" |Condition Register Bitfield 1
(Floating Point Op. Result CR)
| rowspan="4" |Volatile
|1
|FX bit. Copy of FPSCR[FX] after the last floating point instruction. ''Refer to FPSCR table for details.''
|-
|1
|FEX bit. Copy of FPSCR[FEX] after the last floating point instruction. ''Refer to FPSCR table for details.''
|-
|1
|VX bit. Copy of FPSCR[VX] after the last floating point instruction. ''Refer to FPSCR table for details.''
|-
|1
|OX bit. Copy of FPSCR[OX] after the last floating point instruction. ''Refer to FPSCR table for details.''
|-
| rowspan="8" |cr2 - cr7
| rowspan="8" |Condition Register Bitfield 2 - 7
| rowspan="8" |Saved (cr2 - cr4)
Volatile (cr5 - cr7)
| rowspan="2" |1
|''<small>For '''integer''' comparison instructions:</small>'' LT bit. Set to 1 if integer A is less than integer B.
|-
|''<small>For '''floating point''' comparison instructions:</small>'' FL bit (Float Less-than). Set to 1 if float A is less than float B.
|-
| rowspan="2" |1
|''<small>For '''integer''' comparison instructions:</small>'' GT bit. Set to 1 if integer A is greater than integer B.
|-
|''<small>For '''floating point''' comparison instructions:</small>'' FG bit (Float Greater-than). Set to 1 if float A is greater than float B.
|-
| rowspan="2" |1
|''<small>For '''integer''' comparison instructions:</small>'' EQ bit. Set to 1 if both integers compared are equal to each other.
|-
|''<small>For '''floating point''' comparison instructions:</small>'' FE bit (Float Equal). Set to 1 if both floats compared are equal to each other.
|-
| rowspan="2" |1
|''<small>For '''integer''' comparison instructions:</small>'' SO bit = Copy of XER[SO] after the last integer instruction. ''Refer to XER table for details.''
|-
|''<small>For '''floating point''' comparison instructions:</small>'' FU bit (Float Unordered) = One or both of the floats compared is [https://en.wikipedia.org/wiki/NaN NaN] (Not a Number).
|}
{| class="wikitable mw-collapsible mw-collapsed" style="min-width: 200px"
|+Floating Point Status and Control Register (FPSCR)
!Bit Index
!Name
!Attributes
!Bits
!Purpose
|-
|FPSCR[0]
|Floating point eXception summary (FX) bit
|Status Bit + Sticky
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[1]
|Floating point Enabled eXception summary (FEX) bit
| rowspan="2" |Status Bits
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[2]
|inValid operation eXception summary (VX) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[3]
|Overflow eXception (OX) bit
| rowspan="10" |Status Bits + Sticky
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[4]
|Underflow eXception (UX) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[5]
|Zero-divide eXception (ZX) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[6]
|ineXact eXception (XX) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[7]
|inValid operation eXception for "SNaN" (VXSNAN) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[8]
|inValid operation eXception for Infinity Subtracted by Infinity (VXISI) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[9]
|inValid operation eXception for Infinity Divided by Infinity (VXIDI) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[10]
|inValid operation eXception for Zero Divided by Zero (VXZDZ) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[11]
|inValid operation eXception for Infinity Multiplied by Zero (VXIMZ) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[12]
|inValid operation eXception for inValid Comparison (VXVC) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[13]
|Fraction Rounded (FR) bit
| rowspan="3" |Status Bits
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[14]
|Fraction Inexact (FI) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[15-19]
|Floating Point Result Flags (FPRF) bits
|5
|<small><sub>TODO</sub></small>
|-
|FPSCR[20]
|<small>''N/A''</small>
|Reserved
|1
|Reserved by the system.
|-
|FPSCR[21]
|inValid operation eXception for SOFTware request (VXSOFT) bit
| rowspan="3" |Status Bits + Sticky
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[22]
|inValid operation eXception for invalid SQuare RooT (VXSQRT) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[23]
|inValid operation eXception for invalid ConVerted Integer (VXCVI) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[24]
|inValid operation exception Enable (VE) bit
| rowspan="7" |Control Bits
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[25]
|Overflow exception Enable (OE) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[26]
|Underflow exception Enable (UE) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[27]
|Zero-division exception Enable (ZE) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[28]
|ineXact exception Enable (XE) bit
|1
|<small><sub>TODO</sub></small>
|-
|FPSCR[29]
|Non-IEEE mode (NI) bit
|1
|If this bit is set, results need not conform with [https://en.wikipedia.org/wiki/IEEE_754 IEEE754] standards and the other FPSCR bits may have meanings other than those described here and are implementation-specific.
|-
|FPSCR[30-31]
|RouNding control (RN) bits
|2
|00 = Round to nearest
01 = Round toward zero 10 = Round toward +Infinity 11 = Round toward -Infinity
|}
{| class="wikitable mw-collapsible mw-collapsed" style="min-width: 200px"
|+fiXed point Exception Register (XER)
!Bit Index
!Name
!Attributes
!Bits
!Purpose
|-
|XER[0]
|Summary Overflow (SO) bit
|''None''
|1
|Set whenever an instruction (except '''mtspr''') sets the OV bit. Once set, the this bit remains set until it is cleared by an '''mtspr''' instruction (specifying the XER) or an '''mcrxr''' instruction. It is not altered by compare instructions, nor by other instructions (except '''mtspr''' to the XER, and '''mcrxr''') that cannot overflow.
|-
|XER[1]
|OVerflow{{nbsp}}(OV) bit
|''None''
|1
|Set to indicate that an overflow has occurred during execution of an instruction. Add, subtract from, and negate instructions having OE = 1 set the OV bit if the carry out of the MSB is not equal to the carry out of the MSB + 1, and clear it otherwise. Multiply low and divide instructions having OE = 1 set the OV bit if the result cannot be represented in 64 bits ('''mulld''', '''divd''', '''divdu''') or in 32 bits ('''mullw''', '''divw''', '''divwu'''), and clear it otherwise. The OV bit is not altered by compare instructions that cannot overflow (except '''mtspr''' to the XER, and '''mcrxr''').
|-
|XER[2]
|CArry (CA) bit
|''None''
|1
|Set during execution of the following instructions:
- Add carrying, subtract from carrying, add extended, and subtract from extended instructions set it if there is a carry out of the MSB, and clear it otherwise. - Shift right algebraic instructions set it if any 1 bits have been shifted out of a negative operand, and clear it otherwise. The bit is not altered by compare instructions, nor by other instructions that cannot carry (except shift right algebraic, '''mtspr''' to the XER, and '''mcrxr''').
|-
|XER[3-24]
|<small>''N/A''</small>
|Reserved
|22
|Reserved by the system.
|-
|XER[25-31]
|''Unnamed''
|''None''
|7
|This field specifies the number of bytes to be transferred by a Load String Word Indexed ('''lswx''') or STore String Word Indexed ('''stswx''') instruction.
|}
[[Category:Documentation]]
__FORCETOC__

Revision as of 20:01, 23 November 2022

Condition Register (CR)
Sub-register Name Attributes Bits Purpose
cr0 Condition Register Bitfield 0

(Integer Op. Result CR)

Volatile 1 Less Than (LT) bit. Set to 1 if the result of the last integer instruction was negative.
1 Greater Than (GT) bit. Set to 1 if the result of the last integer instruction was positive and non-zero.
1 Equal (EQ) bit. Set to 1 if the result of the last integer instruction was zero.
1 Summary Overflow (SO) bit. Copy of XER[SO] after the last integer instruction. Refer to XER table for details.
cr1 Condition Register Bitfield 1

(Floating Point Op. Result CR)

Volatile 1 FX bit. Copy of FPSCR[FX] after the last floating point instruction. Refer to FPSCR table for details.
1 FEX bit. Copy of FPSCR[FEX] after the last floating point instruction. Refer to FPSCR table for details.
1 VX bit. Copy of FPSCR[VX] after the last floating point instruction. Refer to FPSCR table for details.
1 OX bit. Copy of FPSCR[OX] after the last floating point instruction. Refer to FPSCR table for details.
cr2 - cr7 Condition Register Bitfield 2 - 7 Saved (cr2 - cr4)

Volatile (cr5 - cr7)

1 For integer comparison instructions: LT bit. Set to 1 if integer A is less than integer B.
For floating point comparison instructions: FL bit (Float Less-than). Set to 1 if float A is less than float B.
1 For integer comparison instructions: GT bit. Set to 1 if integer A is greater than integer B.
For floating point comparison instructions: FG bit (Float Greater-than). Set to 1 if float A is greater than float B.
1 For integer comparison instructions: EQ bit. Set to 1 if both integers compared are equal to each other.
For floating point comparison instructions: FE bit (Float Equal). Set to 1 if both floats compared are equal to each other.
1 For integer comparison instructions: SO bit = Copy of XER[SO] after the last integer instruction. Refer to XER table for details.
For floating point comparison instructions: FU bit (Float Unordered) = One or both of the floats compared is NaN (Not a Number).
Floating Point Status and Control Register (FPSCR)
Bit Index Name Attributes Bits Purpose
FPSCR[0] Floating point eXception summary (FX) bit Status Bit + Sticky 1 TODO
FPSCR[1] Floating point Enabled eXception summary (FEX) bit Status Bits 1 TODO
FPSCR[2] inValid operation eXception summary (VX) bit 1 TODO
FPSCR[3] Overflow eXception (OX) bit Status Bits + Sticky 1 TODO
FPSCR[4] Underflow eXception (UX) bit 1 TODO
FPSCR[5] Zero-divide eXception (ZX) bit 1 TODO
FPSCR[6] ineXact eXception (XX) bit 1 TODO
FPSCR[7] inValid operation eXception for "SNaN" (VXSNAN) bit 1 TODO
FPSCR[8] inValid operation eXception for Infinity Subtracted by Infinity (VXISI) bit 1 TODO
FPSCR[9] inValid operation eXception for Infinity Divided by Infinity (VXIDI) bit 1 TODO
FPSCR[10] inValid operation eXception for Zero Divided by Zero (VXZDZ) bit 1 TODO
FPSCR[11] inValid operation eXception for Infinity Multiplied by Zero (VXIMZ) bit 1 TODO
FPSCR[12] inValid operation eXception for inValid Comparison (VXVC) bit 1 TODO
FPSCR[13] Fraction Rounded (FR) bit Status Bits 1 TODO
FPSCR[14] Fraction Inexact (FI) bit 1 TODO
FPSCR[15-19] Floating Point Result Flags (FPRF) bits 5 TODO
FPSCR[20] N/A Reserved 1 Reserved by the system.
FPSCR[21] inValid operation eXception for SOFTware request (VXSOFT) bit Status Bits + Sticky 1 TODO
FPSCR[22] inValid operation eXception for invalid SQuare RooT (VXSQRT) bit 1 TODO
FPSCR[23] inValid operation eXception for invalid ConVerted Integer (VXCVI) bit 1 TODO
FPSCR[24] inValid operation exception Enable (VE) bit Control Bits 1 TODO
FPSCR[25] Overflow exception Enable (OE) bit 1 TODO
FPSCR[26] Underflow exception Enable (UE) bit 1 TODO
FPSCR[27] Zero-division exception Enable (ZE) bit 1 TODO
FPSCR[28] ineXact exception Enable (XE) bit 1 TODO
FPSCR[29] Non-IEEE mode (NI) bit 1 If this bit is set, results need not conform with IEEE754 standards and the other FPSCR bits may have meanings other than those described here and are implementation-specific.
FPSCR[30-31] RouNding control (RN) bits 2 00 = Round to nearest

01 = Round toward zero 10 = Round toward +Infinity 11 = Round toward -Infinity

fiXed point Exception Register (XER)
Bit Index Name Attributes Bits Purpose
XER[0] Summary Overflow (SO) bit None 1 Set whenever an instruction (except mtspr) sets the OV bit. Once set, the this bit remains set until it is cleared by an mtspr instruction (specifying the XER) or an mcrxr instruction. It is not altered by compare instructions, nor by other instructions (except mtspr to the XER, and mcrxr) that cannot overflow.
XER[1] OVerflow (OV) bit None 1 Set to indicate that an overflow has occurred during execution of an instruction. Add, subtract from, and negate instructions having OE = 1 set the OV bit if the carry out of the MSB is not equal to the carry out of the MSB + 1, and clear it otherwise. Multiply low and divide instructions having OE = 1 set the OV bit if the result cannot be represented in 64 bits (mulld, divd, divdu) or in 32 bits (mullw, divw, divwu), and clear it otherwise. The OV bit is not altered by compare instructions that cannot overflow (except mtspr to the XER, and mcrxr).
XER[2] CArry (CA) bit None 1 Set during execution of the following instructions:

- Add carrying, subtract from carrying, add extended, and subtract from extended instructions set it if there is a carry out of the MSB, and clear it otherwise. - Shift right algebraic instructions set it if any 1 bits have been shifted out of a negative operand, and clear it otherwise. The bit is not altered by compare instructions, nor by other instructions that cannot carry (except shift right algebraic, mtspr to the XER, and mcrxr).

XER[3-24] N/A Reserved 22 Reserved by the system.
XER[25-31] Unnamed None 7 This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx) or STore String Word Indexed (stswx) instruction.