PowerPC Special Purpose Registers
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CR[edit | edit source]
Sub-register | Name | Attributes | Bits | Purpose |
---|---|---|---|---|
cr0 | Condition Register Bitfield 0
(Integer Op. Result CR) |
Volatile | 1 | Less Than (LT) bit. Set to 1 if the result of the last integer instruction was negative. |
1 | Greater Than (GT) bit. Set to 1 if the result of the last integer instruction was positive and non-zero. | |||
1 | Equal (EQ) bit. Set to 1 if the result of the last integer instruction was zero. | |||
1 | Summary Overflow (SO) bit. Copy of XER[SO] after the last integer instruction. Refer to XER table for details. | |||
cr1 | Condition Register Bitfield 1
(Floating Point Op. Result CR) |
Volatile | 1 | FX bit. Copy of FPSCR[FX] after the last floating point instruction. Refer to FPSCR table for details. |
1 | FEX bit. Copy of FPSCR[FEX] after the last floating point instruction. Refer to FPSCR table for details. | |||
1 | VX bit. Copy of FPSCR[VX] after the last floating point instruction. Refer to FPSCR table for details. | |||
1 | OX bit. Copy of FPSCR[OX] after the last floating point instruction. Refer to FPSCR table for details. | |||
cr2 - cr7 | Condition Register Bitfield 2 - 7 | Saved (cr2 - cr4)
Volatile (cr5 - cr7) |
1 | For integer comparison instructions: LT bit. Set to 1 if integer A is less than integer B. |
For floating point comparison instructions: FL bit (Float Less-than). Set to 1 if float A is less than float B. | ||||
1 | For integer comparison instructions: GT bit. Set to 1 if integer A is greater than integer B. | |||
For floating point comparison instructions: FG bit (Float Greater-than). Set to 1 if float A is greater than float B. | ||||
1 | For integer comparison instructions: EQ bit. Set to 1 if both integers compared are equal to each other. | |||
For floating point comparison instructions: FE bit (Float Equal). Set to 1 if both floats compared are equal to each other. | ||||
1 | For integer comparison instructions: SO bit = Copy of XER[SO] after the last integer instruction. Refer to XER table for details. | |||
For floating point comparison instructions: FU bit (Float Unordered) = One or both of the floats compared is NaN (Not a Number). |
XER[edit | edit source]
Bit Index | Name | Bits | Purpose |
---|---|---|---|
XER[0] | Summary Overflow (SO) bit | 1 | Set whenever an instruction (except mtspr) sets the OV bit. Once set, this bit remains set until it is cleared by an mtspr instruction (specifying the XER) or an mcrxr instruction. It is not altered by compare instructions, nor by other instructions (except mtspr to the XER, and mcrxr) that cannot overflow. |
XER[1] | OVerflow (OV) bit | 1 | Set to indicate that a signed overflow has occurred during execution of an instruction. "Add", "Subtract from", and "Negate" instructions having OE = 1 (with an o suffix) will set the OV bit if the carry out of the MSB is not equal to the carry out of the (MSB + 1), and clear it otherwise. Multiply low and divide instructions having OE = 1 will set the OV bit if the result cannot be represented in 64 bits (mulld, divd, divdu) or in 32 bits (mullw, divw, divwu), and clear it otherwise. The OV bit is not altered by compare instructions that cannot overflow (except mtspr to the XER, and mcrxr). |
XER[2] | CArry (CA) bit | 1 | Set during execution of the following instructions:
- "Add carrying", "Subtract from carrying", "Add extended", and "Subtract from extended" instructions set CA if there is a carry out of the MSB, and clear it otherwise. - Shift right algebraic instructions set CA if any 1 bits have been shifted out of a negative operand, and clear it otherwise. The bit is not altered by compare instructions, nor by other instructions that cannot carry (except shift right algebraic, mtspr to the XER, and mcrxr). |
XER[3-24] | N/A | 22 | Reserved by the system. |
XER[25-31] | Unnamed | 7 | This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx) or STore String Word Indexed (stswx) instruction. |
FPSCR[edit | edit source]
Bit Index | Name | Attributes | Bits | Purpose |
---|---|---|---|---|
FPSCR[0] | Floating point eXception summary (FX) bit | Status Bit + Sticky | 1 | _{TODO} |
FPSCR[1] | Floating point Enabled eXception summary (FEX) bit | Status Bits | 1 | _{TODO} |
FPSCR[2] | inValid operation eXception summary (VX) bit | 1 | _{TODO} | |
FPSCR[3] | Overflow eXception (OX) bit | Status Bits + Sticky | 1 | _{TODO} |
FPSCR[4] | Underflow eXception (UX) bit | 1 | _{TODO} | |
FPSCR[5] | Zero-divide eXception (ZX) bit | 1 | _{TODO} | |
FPSCR[6] | ineXact eXception (XX) bit | 1 | _{TODO} | |
FPSCR[7] | inValid operation eXception for "SNaN" (VXSNAN) bit | 1 | _{TODO} | |
FPSCR[8] | inValid operation eXception for Infinity Subtracted by Infinity (VXISI) bit | 1 | _{TODO} | |
FPSCR[9] | inValid operation eXception for Infinity Divided by Infinity (VXIDI) bit | 1 | _{TODO} | |
FPSCR[10] | inValid operation eXception for Zero Divided by Zero (VXZDZ) bit | 1 | _{TODO} | |
FPSCR[11] | inValid operation eXception for Infinity Multiplied by Zero (VXIMZ) bit | 1 | _{TODO} | |
FPSCR[12] | inValid operation eXception for inValid Comparison (VXVC) bit | 1 | _{TODO} | |
FPSCR[13] | Fraction Rounded (FR) bit | Status Bits | 1 | _{TODO} |
FPSCR[14] | Fraction Inexact (FI) bit | 1 | _{TODO} | |
FPSCR[15-19] | Floating Point Result Flags (FPRF) bits | 5 | _{TODO} | |
FPSCR[20] | N/A | Reserved | 1 | Reserved by the system. |
FPSCR[21] | inValid operation eXception for SOFTware request (VXSOFT) bit | Status Bits + Sticky | 1 | _{TODO} |
FPSCR[22] | inValid operation eXception for invalid SQuare RooT (VXSQRT) bit | 1 | _{TODO} | |
FPSCR[23] | inValid operation eXception for invalid ConVerted Integer (VXCVI) bit | 1 | _{TODO} | |
FPSCR[24] | inValid operation exception Enable (VE) bit | Control Bits | 1 | _{TODO} |
FPSCR[25] | Overflow exception Enable (OE) bit | 1 | _{TODO} | |
FPSCR[26] | Underflow exception Enable (UE) bit | 1 | _{TODO} | |
FPSCR[27] | Zero-division exception Enable (ZE) bit | 1 | _{TODO} | |
FPSCR[28] | ineXact exception Enable (XE) bit | 1 | _{TODO} | |
FPSCR[29] | Non-IEEE mode (NI) bit | 1 | If this bit is set, results need not conform with IEEE754 standards and the other FPSCR bits may have meanings other than those described here and are implementation-specific. | |
FPSCR[30-31] | RouNding control (RN) bits | 2 | 00 = Round to nearest
01 = Round toward zero 10 = Round toward +Infinity 11 = Round toward -Infinity |
TB[edit | edit source]
Register | Name | Attributes | Bits | Purpose |
---|---|---|---|---|
TBU | Time Base Upper Register | Read-only | 32 | Stores the upper 32 bits of the Time Base value. |
TBL | Time Base Lower Register | Read-only | 32 | Stores the lower 32 bits of the Time Base value. |