Custom Code/PowerPC Assembly Cheatsheet: Difference between revisions
Jhmaster2000 (talk | contribs) m (better description for embed pls) |
Jhmaster2000 (talk | contribs) (improve registers table) |
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if a right shift operation does not specify it is sign-fill, it is implicitly zero-fill by default |
if a right shift operation does not specify it is sign-fill, it is implicitly zero-fill by default |
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if a value is referred to simply as "value" without specifying bit-count, it is implicitly 32 bits (aka a WORD) |
if a value is referred to simply as "value" without specifying bit-count, it is implicitly 32 bits (aka a WORD or INT) |
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C-style casts are used due to being shorter to fit in the small table cells code snippets, but treat them as static_cast<T> |
C-style casts are used due to being shorter to fit in the small table cells code snippets, but treat them as '''static_cast<T>''' |
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<nowiki>#</nowiki> = placeholder |
<nowiki>#</nowiki> = placeholder |
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Line 20: | Line 20: | ||
====== Registers ====== |
====== Registers ====== |
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{| class="wikitable mw-collapsible mw-collapsed" |
{| class="wikitable mw-collapsible mw-collapsed" |
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|+ |
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|+General Purpose Registers (GPRs) |
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!Register |
!Register |
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!Name |
!Name |
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!Purpose |
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!Type |
!Type |
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!Purpose |
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|- |
|- |
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| colspan="4" style="text-align: center;" |'''General Purpose Registers (GPRs)''' |
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|r0 - r31 |
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|Registers 0 to 31 |
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|Store integer values and addresses |
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|TODO |
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|- |
|- |
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| |
|r0 |
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|GPR0 |
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|Floating Point Registers (FPRs) 0 to 31 |
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|Volatile |
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|Store floating point numbers |
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|General purpose, may be used by function linkage |
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|TODO |
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|} |
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{| class="wikitable mw-collapsible mw-collapsed" |
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|+Special Purpose Registers (SPRs) |
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!Register |
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!Name |
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!Purpose |
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!Type |
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|- |
|- |
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| |
|r1 |
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| GPR1 |
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|Condition Register |
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|Unique |
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|Stores a condition (todo explain this better + its subregisters crX) |
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|Stores the stack pointer |
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|TODO |
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|- |
|- |
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| |
|r2 |
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|GPR2 |
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|CounT Register |
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|Unique |
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|Stores the counter of loop iterations for most instructions that perform loops |
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|Reserved for the system |
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|TODO |
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|- |
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|r3 |
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|GPR3 |
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|Volatile |
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|Stores 1st argument passed to function calls and their return value |
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|- |
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|r4 - r10 |
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|GPR4 - GPR10 |
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|Volatile |
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|Store from 2nd to 8th argument passed to function calls |
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|- |
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|r11 - r12 |
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|GPR11 - GPR12 |
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|Volatile |
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|General purpose, may be used by function linkage |
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|- |
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|r13 |
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|GPR13 |
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|Unique |
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|Stores the small data area pointer |
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|- |
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|r14 - r31 |
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|GPR14 - GPR31 |
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|Saved |
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|Store generic integer values and pointers |
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|- |
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| colspan="4" style="text-align: center;" |'''Floating Point Registers (FPRs)''' |
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|- |
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|f0 |
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|FPR0 |
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|Volatile |
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|Store generic floating point numbers |
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|- |
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|f1 |
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|FPR1 |
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|Volatile |
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|Stores 1st float argument passed to function calls and their float return value |
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|- |
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|f2 - f8 |
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|FPR2 - FPR8 |
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|Volatile |
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|Store from 2nd to 8th float argument passed to function calls |
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|- |
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|f9 - f13 |
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|FPR9 - FPR13 |
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|Volatile |
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|Store generic floating point numbers |
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|- |
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|f14 - f30 |
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|FPR14 - FPR30 |
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|Saved |
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|Store generic floating point numbers |
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|- |
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|f31 |
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|FPR31 |
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|Saved |
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|General purpose, used for static chain if needed |
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|- |
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| colspan="4" style="text-align: center;" |'''Special Purpose Registers (SPRs)''' |
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|- |
|- |
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|PC / IAR |
|PC / IAR |
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|Program Counter / Instruction Address Register |
|Program Counter / Instruction Address Register |
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|Unique |
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|Stores the address of the current instruction (Automatically managed by the CPU) |
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|Stores the address of the current instruction (Controlled by the CPU) |
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|TODO |
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|- |
|- |
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|LR |
|LR |
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|Link Register |
|Link Register |
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|Volatile |
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|Stores the return address for some of the branching instructions |
|Stores the return address for some of the branching instructions |
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|- |
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|TODO |
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|CTR |
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|CounT Register |
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|Volatile |
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|Stores the counter of loop iterations for most instructions that perform loops |
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|- |
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|XER |
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|??? |
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|Volatile |
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|??? |
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|- |
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|FPSCR |
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|??? |
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|Volatile |
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|??? |
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|- |
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|cr0 |
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|Condition Register 0 |
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|Volatile |
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|Stores a condition |
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|- |
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|cr1 |
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|Condition Register 1 |
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|Volatile |
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|Stores a condition |
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|- |
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|cr2 - cr4 |
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|Condition Registers 2 - 4 |
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|Saved |
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|Stores a condition |
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|- |
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|cr5 - cr7 |
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|Condition Registers 5 - 7 |
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|Volatile |
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|Stores a condition |
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|} |
|} |
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======External Resources====== |
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*http://class.ece.iastate.edu/arun/CprE281_F05/lab/labw10a/Labw10a_Files/PowerPC%20Assembly%20Quick%20Reference.htm |
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====== External Resources ====== |
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* http://class.ece.iastate.edu/arun/CprE281_F05/lab/labw10a/Labw10a_Files/PowerPC%20Assembly%20Quick%20Reference.htm |
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*https://jimkatz.github.io/powerpc_for_dummies (very incomplete, has mistakes) |
*https://jimkatz.github.io/powerpc_for_dummies (very incomplete, has mistakes) |
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* |
*http://wiibrew.org/wiki/Assembler_Tutorial (also has missing instructions but way more accurate and better worded) |
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*https://fail0verflow.com/media/files/ppc_750cl.pdf (official instruction set docs, hard to navigate/search) |
*https://fail0verflow.com/media/files/ppc_750cl.pdf (official instruction set docs, hard to navigate/search) |
||
*http://personal.denison.edu/~bressoud/cs281-s07/ppc_instructions.pdf (similar to the above but stripped of all pages not documenting instructions, easier to search, missing instructions though) |
*http://personal.denison.edu/~bressoud/cs281-s07/ppc_instructions.pdf (similar to the above but stripped of all pages not documenting instructions, easier to search, missing instructions though) |
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====== |
======Pseudocode Typedefs====== |
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<syntaxhighlight lang="c++"> |
<syntaxhighlight lang="c++"> |
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typedef unsigned int uint; // 32 bit value |
typedef unsigned int uint; // 32 bit value |
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Line 81: | Line 164: | ||
</syntaxhighlight> |
</syntaxhighlight> |
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=== Instructions |
=== Instructions=== |
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{| class="wikitable" |
{| class="wikitable" |
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|- |
|- |
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!Instruction |
!Instruction |
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!Name |
!Name |
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!Parameters |
!Parameters |
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|<code>rA, rB, iX₁₆</code> |
|<code>rA, rB, iX₁₆</code> |
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|<code>rA = rB + (iX << 16)</code> |
|<code>rA = rB + (iX << 16)</code> |
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|Adds the values of rB and (iX << 16) together and stores the result in rA |
|Adds the values of rB and (iX << 16) together and stores the result in rA |
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|- |
|- |
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|<code>and</code> |
|<code>and</code> |
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|AND Operation |
| AND Operation |
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|<code>rA, rB, rC</code> |
|<code>rA, rB, rC</code> |
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|<code>rA = rB & rC</code> |
|<code>rA = rB & rC</code> |
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Line 115: | Line 198: | ||
|- |
|- |
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|<code>andc</code> |
|<code>andc</code> |
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|AND Complement |
|AND Complement |
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|<code>rA, rB, rC</code> |
|<code>rA, rB, rC</code> |
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|<code>rA = rB & ~rC</code> |
|<code>rA = rB & ~rC</code> |
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Line 130: | Line 213: | ||
|<code>rA, rB, uiX₁₆</code> |
|<code>rA, rB, uiX₁₆</code> |
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|<code>rA = rB & (uiX << 16)</code> |
|<code>rA = rB & (uiX << 16)</code> |
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|Performs an AND operation on rB and (uiX << 16) then stores the result in rA |
|Performs an AND operation on rB and (uiX << 16) then stores the result in rA |
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|- |
|- |
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|<code>b</code> |
|<code>b</code> |
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Line 197: | Line 280: | ||
|- |
|- |
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|<code>bnl</code> |
|<code>bnl</code> |
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|Branch if Not Less than |
| Branch if Not Less than |
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| |
| |
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| |
| |
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|<code>bun</code> |
|<code>bun</code> |
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|Branch if UNordered |
|Branch if UNordered |
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|??? |
|??? |
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|??? |
|??? |
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|Unknown |
|Unknown |
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|<code>bnu</code> |
|<code>bnu</code> |
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|Branch if Not Unordered |
|Branch if Not Unordered |
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|??? |
| ??? |
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|??? |
|??? |
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|Unknown |
|Unknown |
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Line 281: | Line 364: | ||
|- |
|- |
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|<code>cntlzw</code> |
|<code>cntlzw</code> |
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|CouNT Leading Zeros Word |
| CouNT Leading Zeros Word |
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| |
| |
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| |
| |
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Line 293: | Line 376: | ||
|- |
|- |
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|<code>eqv</code> |
|<code>eqv</code> |
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|EQuiValent |
| EQuiValent |
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|<code>rA, rB, rC</code> |
|<code>rA, rB, rC</code> |
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|<code>rA = rB == rC</code> |
|<code>rA = rB == rC</code> |
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Line 305: | Line 388: | ||
|- |
|- |
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|<code>extsh</code> |
|<code>extsh</code> |
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|EXTend Sign Halfword |
|EXTend Sign Halfword |
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|<code>rA, rB</code> |
|<code>rA, rB</code> |
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|<code>rA = (int16_t)rB</code> |
|<code>rA = (int16_t)rB</code> |
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Line 311: | Line 394: | ||
|- |
|- |
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|<code>lbz</code> |
|<code>lbz</code> |
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|Load Byte Zero-fill |
|Load Byte Zero-fill |
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|<code>rA, iX₁₆(rB)</code> |
|<code>rA, iX₁₆(rB)</code> |
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|<code>rA = (ubyte)(*(rB + iX))</code> |
|<code>rA = (ubyte)(*(rB + iX))</code> |
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Line 355: | Line 438: | ||
|Loads the value at the address (rB + rC) into rA |
|Loads the value at the address (rB + rC) into rA |
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|- |
|- |
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|<code>lmw</code> * |
|<code>lmw</code> * |
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|Load Multiple Words |
|Load Multiple Words |
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|<code>rA, iX₁₆(rB)</code> |
|<code>rA, iX₁₆(rB)</code> |
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Line 393: | Line 476: | ||
|<code>rA</code> |
|<code>rA</code> |
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|<code>CTR = rA</code> |
|<code>CTR = rA</code> |
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|Copies the value of rA into the CTR |
| Copies the value of rA into the CTR |
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|- |
|- |
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|<code>mtspr</code> |
|<code>mtspr</code> |
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Line 429: | Line 512: | ||
|<code>rA, rB</code> |
|<code>rA, rB</code> |
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|<code>rA = ~rB</code> |
|<code>rA = ~rB</code> |
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|Stores in rA the result of negated rB |
|Stores in rA the result of negated rB |
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|- |
|- |
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|<code>or</code> |
|<code>or</code> |
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Line 444: | Line 527: | ||
|- |
|- |
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|<code>ori</code> |
|<code>ori</code> |
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|OR Immediate |
| OR Immediate |
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|<code>rA, rB, iX₁₆</code> |
|<code>rA, rB, iX₁₆</code> |
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| `rA="rB" |<code><nowiki>rA = rB | iX</nowiki></code> |
| `rA="rB" |<code><nowiki>rA = rB | iX</nowiki></code> |
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Line 462: | Line 545: | ||
rA = (rB << iX) | (rB >> (32 - iX)) & mask; |
rA = (rB << iX) | (rB >> (32 - iX)) & mask; |
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</syntaxhighlight> |
</syntaxhighlight> |
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|Rotates the value in rB by iX bits to the left |
| Rotates the value in rB by iX bits to the left |
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The result of the above is AND'ed with the mask specified by iY and iZ |
The result of the above is AND'ed with the mask specified by iY and iZ |
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Line 476: | Line 559: | ||
|<code>iX₇</code> |
|<code>iX₇</code> |
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|N/A |
|N/A |
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|Calls upon the system to perform a service identified by iX |
| Calls upon the system to perform a service identified by iX |
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|- |
|- |
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|<code>slw</code> |
|<code>slw</code> |
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Line 517: | Line 600: | ||
|- |
|- |
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|<code>stb</code> |
|<code>stb</code> |
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|STore Byte |
|STore Byte |
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|<code>rA, iX₁₆(rB)</code> |
|<code>rA, iX₁₆(rB)</code> |
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|<code>*(rB + iX) = (ubyte)rA</code> |
|<code>*(rB + iX) = (ubyte)rA</code> |
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Line 529: | Line 612: | ||
|- |
|- |
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|<code>stw</code> |
|<code>stw</code> |
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|STore Word |
|STore Word |
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|<code>rA, iX₁₆(rB)</code> |
|<code>rA, iX₁₆(rB)</code> |
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|<code>*(rB + iX) = rA</code> |
|<code>*(rB + iX) = rA</code> |
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|Stores the value of rA at the memory address (rB + iX) |
| Stores the value of rA at the memory address (rB + iX) |
||
|- |
|- |
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|<code>stwu</code> |
|<code>stwu</code> |
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Line 543: | Line 626: | ||
|- |
|- |
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|<code>stwx</code> |
|<code>stwx</code> |
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|STore Word indeXed |
| STore Word indeXed |
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|<code>rA, rB, rC</code> |
|<code>rA, rB, rC</code> |
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|<code>*(rB + rC) = rA</code> |
|<code>*(rB + rC) = rA</code> |
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|Stores the value of rA at the memory address (rB + rC) |
|Stores the value of rA at the memory address (rB + rC) |
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|- |
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|<code>stmw</code> * |
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|STore Multiple Words |
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| |
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| |
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| |
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|- |
|- |
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|<code>xor</code> |
|<code>xor</code> |
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|XOR operation |
| XOR operation |
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|<code>rA, rB, rC</code> |
|<code>rA, rB, rC</code> |
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|<code>rA = rB ^ rC</code> |
|<code>rA = rB ^ rC</code> |
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Line 555: | Line 644: | ||
|- |
|- |
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|<code>xori</code> |
|<code>xori</code> |
||
|XOR Immediate |
| XOR Immediate |
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|<code>rA, rB, iX₁₆</code> |
|<code>rA, rB, iX₁₆</code> |
||
|<code>rA = rB ^ iX</code> |
|<code>rA = rB ^ iX</code> |
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Line 569: | Line 658: | ||
__NOTOC__ |
__NOTOC__ |
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__NOEDITSECTION__ |
__NOEDITSECTION__ |
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[[Category:Documentation]] |
Revision as of 07:35, 4 September 2022
Instructions, registers and general info cheatsheet for PowerPC 32-bit Big Endian Assembly architecture used by the Wii U.
// WIP Draft
if a right shift operation does not specify it is sign-fill, it is implicitly zero-fill by default
if a value is referred to simply as "value" without specifying bit-count, it is implicitly 32 bits (aka a WORD or INT)
C-style casts are used due to being shorter to fit in the small table cells code snippets, but treat them as static_cast<T>
# = placeholder
r# = register
i# = immediate (the subscript numbers next to it is it's size in bits)
ui# = unsigned immediate (above is signed)
* = unsure of functionality
Registers
Register | Name | Type | Purpose |
---|---|---|---|
General Purpose Registers (GPRs) | |||
r0 | GPR0 | Volatile | General purpose, may be used by function linkage |
r1 | GPR1 | Unique | Stores the stack pointer |
r2 | GPR2 | Unique | Reserved for the system |
r3 | GPR3 | Volatile | Stores 1st argument passed to function calls and their return value |
r4 - r10 | GPR4 - GPR10 | Volatile | Store from 2nd to 8th argument passed to function calls |
r11 - r12 | GPR11 - GPR12 | Volatile | General purpose, may be used by function linkage |
r13 | GPR13 | Unique | Stores the small data area pointer |
r14 - r31 | GPR14 - GPR31 | Saved | Store generic integer values and pointers |
Floating Point Registers (FPRs) | |||
f0 | FPR0 | Volatile | Store generic floating point numbers |
f1 | FPR1 | Volatile | Stores 1st float argument passed to function calls and their float return value |
f2 - f8 | FPR2 - FPR8 | Volatile | Store from 2nd to 8th float argument passed to function calls |
f9 - f13 | FPR9 - FPR13 | Volatile | Store generic floating point numbers |
f14 - f30 | FPR14 - FPR30 | Saved | Store generic floating point numbers |
f31 | FPR31 | Saved | General purpose, used for static chain if needed |
Special Purpose Registers (SPRs) | |||
PC / IAR | Program Counter / Instruction Address Register | Unique | Stores the address of the current instruction (Controlled by the CPU) |
LR | Link Register | Volatile | Stores the return address for some of the branching instructions |
CTR | CounT Register | Volatile | Stores the counter of loop iterations for most instructions that perform loops |
XER | ??? | Volatile | ??? |
FPSCR | ??? | Volatile | ??? |
cr0 | Condition Register 0 | Volatile | Stores a condition |
cr1 | Condition Register 1 | Volatile | Stores a condition |
cr2 - cr4 | Condition Registers 2 - 4 | Saved | Stores a condition |
cr5 - cr7 | Condition Registers 5 - 7 | Volatile | Stores a condition |
External Resources
- http://class.ece.iastate.edu/arun/CprE281_F05/lab/labw10a/Labw10a_Files/PowerPC%20Assembly%20Quick%20Reference.htm
- https://jimkatz.github.io/powerpc_for_dummies (very incomplete, has mistakes)
- http://wiibrew.org/wiki/Assembler_Tutorial (also has missing instructions but way more accurate and better worded)
- https://fail0verflow.com/media/files/ppc_750cl.pdf (official instruction set docs, hard to navigate/search)
- http://personal.denison.edu/~bressoud/cs281-s07/ppc_instructions.pdf (similar to the above but stripped of all pages not documenting instructions, easier to search, missing instructions though)
Pseudocode Typedefs
typedef unsigned int uint; // 32 bit value
typedef signed int sint; // 32 bit value
typedef unsigned short ushort; // 16 bit value
typedef signed short sshort; // 16 bit value
typedef unsigned char ubyte; // 8 bit value
typedef signed char sbyte; // 8 bit value
Instructions
Instruction | Name | Parameters | Pseudocode Equivalent | Additional Info |
---|---|---|---|---|
add
|
ADD operation | rA, rB, rC
|
rA = rB + rC
|
Adds the values of rB and rC together and stores the result in rA |
addi
|
ADD Immediate | rA, rB, iX₁₆
|
rA = rB + iX
|
Adds the values of rB and iX together and stores the result in rA |
addis
|
ADD Immediate Shifted | rA, rB, iX₁₆
|
rA = rB + (iX << 16)
|
Adds the values of rB and (iX << 16) together and stores the result in rA |
and
|
AND Operation | rA, rB, rC
|
rA = rB & rC
|
Performs an AND operation on rB and rC then stores the result in rA |
andc
|
AND Complement | rA, rB, rC
|
rA = rB & ~rC
|
Performs an AND operation on rB and negated rC then stores the result in rA |
andi.
|
AND Immediate | rA, rB, uiX₁₆
|
rA = rB & uiX
|
Performs an AND operation on rB and uiX then stores the result in rA |
andis.
|
AND Immediate Shifted | rA, rB, uiX₁₆
|
rA = rB & (uiX << 16)
|
Performs an AND operation on rB and (uiX << 16) then stores the result in rA |
b
|
Branch | iX₂₄
|
goto LABEL
|
Jumps from the current address to IAR + iX, either up or down |
bl
|
Branch and Link | iX₂₄
|
((void (*)())IAR + iX)()
|
Jumps from the current address to IAR + iX, either up or down
Also stores the address of the instruction directly below it in LR This is the most common instruction to use for calling a function |
blr
|
Branch to Link Register | N/A | return
|
Jumps from the current address to the address stored in LR
This is essentially the return statement of a function |
beq
|
Branch if EQual | |||
bne
|
Branch if Not Equal | |||
bgt
|
Branch if Greater Than | |||
blt
|
Branch if Less Than | |||
ble
|
Branch if Less than or Equal | |||
bge
|
Branch if Greater than or Equal | |||
bng
|
Branch if Not Greater than | |||
bnl
|
Branch if Not Less than | |||
bso
|
Branch if Summary Overflow | ??? | ??? | Unknown |
bns
|
Branch if Not Summary overflow | ??? | ??? | Unknown |
bun
|
Branch if UNordered | ??? | ??? | Unknown |
bnu
|
Branch if Not Unordered | ??? | ??? | Unknown |
bctr
|
Branch to CounT Register | |||
bctrl
|
Branch to CounT Register and Link | |||
bdnz
|
Branch if Decremented count register Not Zero | |||
bdnzt
|
Branch if Decremented count register Not Zero and if condition True | |||
bdnzf
|
Branch if Decremented count register Not Zero and if condition False | |||
bdz
|
Branch if Decremented count register Zero | |||
cmp
|
CoMPare | |||
cmpwi
|
CoMPare Word Immediate | |||
cmplwi
|
CoMPare Logical Word Immediate | |||
cntlzw
|
CouNT Leading Zeros Word | |||
eieio
|
Enforce In-order Execution of I/O | ??? | ??? | Unknown |
eqv
|
EQuiValent | rA, rB, rC
|
rA = rB == rC
|
Compares if the values of rB and rC are equal and stores the result in rA (?) |
extsb
|
EXTend Sign Byte | rA, rB
|
rA = (int8_t)rB
|
Fills the upper 24 bits of rB's value with the sign bit of the stored 8 bit value |
extsh
|
EXTend Sign Halfword | rA, rB
|
rA = (int16_t)rB
|
Fills the upper 16 bits of rB's value with the sign bit of the stored 16 bit value |
lbz
|
Load Byte Zero-fill | rA, iX₁₆(rB)
|
rA = (ubyte)(*(rB + iX))
|
Loads the 8 bit value at the address (rB + iX) into rA |
lhz
|
Load Halfword Zero-fill | rA, iX₁₆(rB)
|
rA = (ushort)(*(rB + iX))
|
Loads the 16 bit value at the address (rB + iX) into rA |
li
|
Load Immediate | rA, iX₁₆
|
rA = iX
|
Loads iX into rA |
lis
|
Load Immediate Shifted | rA, iX₁₆
|
rA = rA | (iX << 16)
|
Loads iX into the upper 16 bits of rA |
lwz
|
Load Word Zero-fill | rA, iX₁₆(rB)
|
rA = *(rB + iX)
|
Loads the value at the address (rB + iX) into rA |
lwzu
|
Load Word Zero Update | rA, iX₁₆(rB)
|
rA = *(rB + iX);
rB = rB + iX;
|
Loads the value at the address (rB + iX) into rA Then loads rB with the address (rB + iX) |
lwzx
|
Load Word Zero indeXed | rA, rB, rC
|
rA = *(rB + rC)
|
Loads the value at the address (rB + rC) into rA |
lmw *
|
Load Multiple Words | rA, iX₁₆(rB)
|
int EA = rB + iX;
int N = rA;
do {
GPR[N] = *(EA);
EA = EA + 4;
N = N + 1;
} while (N <= 31);
|
Loads GPR[rA] to r31 with the value at the address (rB + iX + N),
where N starts at 0 and increments by 4 for each register loaded.
|
mr
|
Move Register | rA, rB
|
rA = rB
|
Copies the value of rB into rA (Despite the instruction name, rB is preserved) |
mflr
|
Move From Link Register | rA
|
rA = LR
|
Copies the value of LR into rA |
mtlr
|
Move To Link Register | rA
|
LR = rA
|
Copies the value of rA into the LR |
mtctr
|
Move To CounT Register | rA
|
CTR = rA
|
Copies the value of rA into the CTR |
mtspr
|
Move To Special Purpose Register | SPR, rA
|
SPR[SPR] = rA
|
Copies the value of rA into the special purpose register SPR |
mulli
|
MULtiply Low Immediate | rA, rB, iX₁₆
|
rA = rB * iX
|
Multiplies the value of rB by iX and stores the result in rA |
nand
|
NAND operation | rA, rB, rC
|
rA = ~(rB & rC)
|
Stores in rA the negated result of (rB & rC) |
neg
|
NEGate | rA, rB
|
rA = ~rB + 1
|
Stores in rA the result of negated rB with 1 added to it's value afterwards |
nor
|
NOR operation | rA, rB, rC
|
rA = ~(rB | rC)
|
Stores in rA the negated result of (rB | rC) |
not
|
NOT operation | rA, rB
|
rA = ~rB
|
Stores in rA the result of negated rB |
or
|
OR operation | rA, rB, rC
|
rA = rB | rC
|
Stores in rA the result of (rB | rC) |
orc
|
OR Complement | rA, rB, rC
|
rA = rB | ~rC
|
Stores in rA the result of (rB | ~rC) |
ori
|
OR Immediate | rA, rB, iX₁₆
|
rA = rB | iX
|
Stores in rA the result of (rB | iX) |
oris
|
OR Immediate Shifted | rA, rB, iX₁₆
|
rA = rB | (iX << 16)
|
Stores in rA the result of (rB | (iX << 16)) |
rlwinm
|
Rotate Left Word Immediate aNd Mask | rA, rB, iX₅, iY₅, iZ₅
|
uint mask = ((uint)-1) << (31 - iZ + iY) >> iY;
rA = (rB << iX) | (rB >> (32 - iX)) & mask;
|
Rotates the value in rB by iX bits to the left
The result of the above is AND'ed with the mask specified by iY and iZ iY specifies the starting bit of the 1-bits in the mask (0-indexed) iZ specifies the end bit of the 1-bits in the mask (0-indexed) The final result is stored in rA |
sc
|
System Call | iX₇
|
N/A | Calls upon the system to perform a service identified by iX |
slw
|
Shift Left Word | rA, rB, rC
|
rA = rB << rC
|
Shifts the value in rB by the value in rC to the left and stores the result in rA |
slwi
|
Shift Left Word Immediate | rA, rB, iX₅
|
rA = rB << iX
|
Shifts the value in rB by iX to the left and stores the result in rA |
srw
|
Shift Right Word | rA, rB, rC
|
rA = (unsigned)rB >> rC
|
Shifts the value in rB by the value in rC to the right and stores the result in rA |
srwi
|
Shift Right Word Immediate | rA, rB, iX₅
|
rA = (unsigned)rB >> iX
|
Shifts the value in rB by iX to the right and stores the result in rA |
sraw
|
Shift Right Algebraic Word | rA, rB, rC
|
rA = (signed)rB >> rC
|
Shifts the value in rB by the value in rC to the right and stores the result in rA
Unlike regular zero-fill right shift operations, this one sign-fills the vacant bits |
srawi
|
Shift Right Algebraic Word Immediate | rA, rB, iX₅
|
rA = (signed)rB >> iX
|
Shifts the value in rB by iX to the right and stores the result in rA
Unlike regular zero-fill right shift operations, this one sign-fills the vacant bits |
stb
|
STore Byte | rA, iX₁₆(rB)
|
*(rB + iX) = (ubyte)rA
|
Stores the 8 bit value of rA at the memory address (rB + iX) |
sth
|
STore Halfword | rA, iX₁₆(rB)
|
*(rB + iX) = (ushort)rA
|
Stores the 16 bit value of rA at the memory address (rB + iX) |
stw
|
STore Word | rA, iX₁₆(rB)
|
*(rB + iX) = rA
|
Stores the value of rA at the memory address (rB + iX) |
stwu
|
STore Word And Update | rA, iX₁₆(rB)
|
*(rB + iX) = rA
|
Stores the value of rA at the memory address (rB + iX)
Stores the computed address (rB + iX) into rB |
stwx
|
STore Word indeXed | rA, rB, rC
|
*(rB + rC) = rA
|
Stores the value of rA at the memory address (rB + rC) |
stmw *
|
STore Multiple Words | |||
xor
|
XOR operation | rA, rB, rC
|
rA = rB ^ rC
|
Performs an XOR operation on rB and rC then stores the result in rA |
xori
|
XOR Immediate | rA, rB, iX₁₆
|
rA = rB ^ iX
|
Performs an XOR operation on rB and iX then stores the result in rA |
xoris
|
XOR Immediate Shifted | rA, rB, iX₁₆
|
rA = rB ^ (iX << 16)
|
Performs an XOR operation on rB and (iX << 16) then stores the result in rA |