Custom Code/PowerPC Assembly Cheatsheet

// WIP Draft

if a right shift operation does not specify it is sign-fill, it is implicitly zero-fill by default

# = placeholder

r# = register

i# = immediate (the subscript numbers next to it is it's size in bits)

ui# = unsigned immediate (above is signed)

* = unsure of functionality

Registers

General Purpose Registers (GPRs)

Register	Name	Purpose	Type
r0 - r31	Registers 0 to 31	Store stuff	TODO
f0 - f31	Floating Point Registers (FPRs) 0 to 31	Store floating point numbers	TODO

Special Purpose Registers (SPRs)

Register	Name	Purpose
CR	Condition Register	Stores a condition (todo explain this better + its subregisters crX)
CTR	CounT Register	Stores the counter of loop iterations for most instructions that perform loops
PC / IAR	Program Counter / Instruction Address Register	Stores the address of the current instruction (Automatically managed by the CPU)
LR	Link Register	Stores a return address for some of the branching instructions

External Resources

• https://jimkatz.github.io/powerpc_for_dummies (very incomplete, has mistakes)
• http://wiibrew.org/wiki/Assembler_Tutorial#Load_and_Store_Instructions (also has missing instructions but way more accurate and better worded)
• https://fail0verflow.com/media/files/ppc_750cl.pdf (official instruction set docs, hard to navigate/search)

Pseudocode Typedefs

typedef unsigned int uint;
typedef signed int sint;
typedef unsigned short ushort;
typedef signed short sshort;
typedef unsigned char ubyte;
typedef signed char sbyte;

Instruction	Name	Parameters	Pseudocode Equivalent	Additional Info
add	ADD operation	rA, rB, rC	rA = rB + rC	Adds the values of rB and rC together and stores the result in rA
addi	ADD Immediate	rA, rB, iX₁₆	rA = rB + iX	Adds the values of rB and iX together and stores the result in rA
addis	ADD Immediate Shifted	rA, rB, iX₁₆	rA = rB + (iX << 16)	Adds the values of rB and (iX << 16) together and stores the result in rA
and	AND Operation	rA, rB, rC	rA = rB & rC	Performs an AND operation on rB and rC then stores the result in rA
andc	AND Complement	rA, rB, rC	rA = rB & ~rC	Performs an AND operation on rB and negated rC then stores the result in rA
andi.	AND Immediate	rA, rB, uiX₁₆	rA = rB & uiX	Performs an AND operation on rB and uiX then stores the result in rA
andis.	AND Immediate Shifted	rA, rB, uiX₁₆	rA = rB & (uiX << 16)	Performs an AND operation on rB and (uiX << 16) then stores the result in rA
b	Branch	iX₂₄	goto LABEL	Jumps from the current address to IAR + iX, either up or down
bl	Branch and Link	iX₂₄	((void (*)())IAR + iX)()	Jumps from the current address to IAR + iX, either up or down Also stores the address of the instruction directly below it in LR This is the most common instruction to use for calling a function
blr	Branch to Link Register	N/A	return	Jumps from the current address to the address stored in LR This is essentially the return statement of a function
beq	Branch if EQual
bne	Branch if Not Equal
bgt	Branch if Greater Than
blt	Branch if Less Than
ble	Branch if Less than or Equal
bge	Branch if Greater than or Equal
bng	Branch if Not Greater than
bnl	Branch if Not Less than
bso	Branch if Summary Overflow	???	???	Unknown
bns	Branch if Not Summary overflow	???	???	Unknown
bun	Branch if UNordered	???	???	Unknown
bnu	Branch if Not Unordered	???	???	Unknown
bctr	Branch to CounT Register
bctrl	Branch to CounT Register and Link
bdnz	Branch if Decremented count register Not Zero
bdnzt	Branch if Decremented count register Not Zero and if condition True
bdnzf	Branch if Decremented count register Not Zero and if condition False
bdz	Branch if Decremented count register Zero
cmp	CoMPare
cmpwi	CoMPare Word Immediate
cmplwi	CoMPare Logical Word Immediate
cntlzw	CouNT Leading Zeros Word
eieio	Enforce In-order Execution of I/O
eqv	EQuiValent	rA, rB, rC	rA = rB == rC
extsb	EXTend Sign Byte	rA, rB	rA = (int8_t)rB
extsh	EXTend Sign Halfword	rA, rB	rA = (int16_t)rB
li	Load Immediate	rA, iX₁₆	rA = iX	Loads iX into rA
lis	Load Immediate Shifted	rA, iX₁₆	rA = rA | (iX << 16)	Loads iX into the upper 16 bits of rA
lwz	Load Word Zero	rA, iX₁₆(rB)	rA = *(rB + iX)	Loads the value at the address (rB + iX) into rA
lwzu	Load Word Zero Update	rA, iX₁₆(rB)	rA = *(rB + iX); rB = rB + iX;	Loads the value at the address (rB + iX) into rA Then loads rB with the address (rB + iX)
lwzx	Load Word Zero indeXed	rA, rB, rC	rA = *(rB + rC)	Loads the value at the address (rB + rC) into rA
lmw *	Load Multiple Words	rA, iX₁₆(rB)	int EA = rB + iX; int N = rA; do { GPR[N] = *(EA); EA = EA + 4; N = N + 1; } while (N <= 31);	Loads GPR[rA] to r31 with the value at the address (rB + iX + N), where N starts at 0 and increments by 4 for each register loaded. Example: Assume r0 = 29 and r1 = 0x20000000 lmw r0, 0x20(r1) This will load the following registers like so: r29 = *(0x20000020) r30 = *(0x20000024) r31 = *(0x20000028)
mr	Move Register	rA, rB	rA = rB	Copies the value of rB into rA (Despite the instruction name, rB is preserved)
mflr	Move From Link Register
mtlr	Move To Link Register
mtctr	Move To CounT Register
mtspr	Move To Special Purpose Register
mulli	MULtiply Low Immediate
nand	NAND operation	rA, rB, rC	rA = ~(rB & rC)
neg	NEGate	rA, rB	rA = ~rB + 1
nor	NOR operation	rA, rB, rC	rA = ~(rB | rC)
not	NOT operation	rA, rB	rA = ~rB
or	OR operation	rA, rB, rC	rA = rB | rC
orc	OR Complement	rA, rB, rC	rA = rB | ~rC
ori	OR Immediate	rA, rB, iX₁₆	rA = rB | iX
oris	OR Immediate Shifted	rA, rB, iX₁₆	rA = rB | (iX << 16)
rlwinm	Rotate Left Word Immediate aNd Mask	rA, rB, iX₅, iY₅, iZ₅	uint mask = ((uint)-1) << (31 - iZ + iY) >> iY; rA = (rB << iX) | (rB >> (32 - iX)) & mask;	Rotates the value in rB by iX bits to the left The result of the above is AND'ed with the mask specified by iY and iZ iY specifies the starting bit of the 1-bits in the mask (0-indexed) iZ specifies the end bit of the 1-bits in the mask (0-indexed) The final result is stored in rA
sc	System Call	iX₇	N/A	Calls upon the system to perform a service identified by iX
slw	Shift Left Word	rA, rB, rC	rA = rB << rC	Shifts the value in rB by the value in rC to the left and stores the result in rA
slwi	Shift Left Word Immediate	rA, rB, iX₅	rA = rB << iX	Shifts the value in rB by iX to the left and stores the result in rA
srw	Shift Right Word	rA, rB, rC	rA = (unsigned)rB >> rC	Shifts the value in rB by the value in rC to the right and stores the result in rA
srwi	Shift Right Word Immediate	rA, rB, iX₅	rA = (unsigned)rB >> iX	Shifts the value in rB by iX to the right and stores the result in rA
sraw	Shift Right Algebraic Word	rA, rB, rC	rA = (signed)rB >> rC	Shifts the value in rB by the value in rC to the right and stores the result in rA Unlike regular zero-fill right shift operations, this one sign-fills the vacant bits
srawi	Shift Right Algebraic Word Immediate	rA, rB, iX₅	rA = (signed)rB >> iX	Shifts the value in rB by iX to the right and stores the result in rA Unlike regular zero-fill right shift operations, this one sign-fills the vacant bits
stw	STore Word	rA, iX₁₆(rB)	*(rB + iX) = rA	Stores the value of rA at the memory address (rB + iX)
stwu	STore Word And Update	rA, iX₁₆(rB)	*(rB + iX) = rA rB = rB + iX	Stores the value of rA at the memory address (rB + iX) Stores the computed address (rB + iX) into rB
stwx	STore Word indeXed	rA, rB, rC	*(rB + rC) = rA	Stores the value of rA at the memory address (rB + rC)
xor	XOR operation	rA, rB, rC	rA = rB ^ rC	Performs an XOR operation on rB and rC then stores the result in rA
xori	XOR Immediate	rA, rB, iX₁₆	rA = rB ^ iX	Performs an XOR operation on rB and iX then stores the result in rA
xoris	XOR Immediate Shifted	rA, rB, iX₁₆	rA = rB ^ (iX << 16)	Performs an XOR operation on rB and (iX << 16) then stores the result in rA